1. Field of the Invention
The present invention relates to integrated circuits (ICs), and more particularly to an IC including a high performance metal stacked inductor that is integrated into a semiconductor interconnect structure
2. Background of the Invention
In the semiconductor industry, digital and analog circuits, including complex microprocessors and operational amplifiers, have been successfully implemented in silicon-based integrated circuits (ICs). Such Si-based ICs typically include active devices such as, for example, bipolar transistors and field effect transistors (FETs), diodes, and passive devices, including resistors, capacitors, and inductors.
Attempts to miniaturize radio frequency (RF) circuits, however, remain a challenge. RF circuits are generally employed in cellular phones, wireless modems, PDAs, and other types of communication equipment. The miniaturization problem is a result of the difficulty in producing a good inductor in silicon technologies which is suitable for RF applications at widely used microwave frequencies from 900 MHz to 2.4 GHz.
Monolithic microwave integrated circuits (MMICs), which are rapidly outpacing discrete ICs in mobile wireless communication products, require high-Q (quality factor) passive components, such as inductors and capacitors, to be able to realize integrated filters and matching sections with small insertion losses.
If conventional silicon technology is used, e.g., BiCMOS, the inductor is clearly the performance and density limiting passive element. While the quality factor Q of an integrated inductor can be improved by modifying the interconnect technology by switching from AlCu to Cu or Au interconnects, the area consumption of the inductor structure is difficult to reduce.
It is well known that the direct current (DC) resistance of a metal line that forms a spiral inductor is a major contributor to the inductor Q degradation. One way to reduce this effect is to use wide metal line widths. However, such an approach increases the inductor area and the parasitic capacitance associated with the structure. Wider metal line widths within a spiral inductor are also subject to frequency dependent loss mechanisms related to eddy current generation within the metal lines (typically called “proximity effect”). Wider and more closely spaced spiral lines will be subject to increased proximity effect over narrower, more widely spaced lines.
The large inductor area limits the miniaturization that can be achieved. The combined negative contributions of parasitic capacitance associated with the large area (lower self resonance frequency), and proximity effects from wide metal lines (increasing frequency dependent loss) further limit the useful frequency range.
A standard feature in present day very large scale integration (VLSI) is the use of multi-level interconnects for inductor integration. Using this technology, some have shunted several layers of metal together to “simulate” a thicker metal layer than achievable in AlCu interconnect technology. See, for example, U.S. Pat. No. 5,446,311 to Ewen, et al. Shunted inductors represent an improvement over the previous prior art.
A typical prior art dual-metal inductor of the type described in the Ewen, et al. disclosure is shown, for example, in FIG. 1. Specifically, FIG. 1 shows a prior art dualmetal inductor 10 that comprises a top metal wire inductor 16 in the MA level that is connected by via 14 to a bottom metal wire inductor 12. The bottom metal wire inductor 12 is connected by another via 14″ to a termination metal level 11. The dual-metal inductor 10 is located in an interlevel or intralevel dielectric (not specifically labeled) of an interconnect structure.
In the prior art dual-metal inductor 10 shown in FIG. 1, the top metal wire inductor 16 is typically an Al wire having a thickness of about 4 μm, and the bottom metal wire inductor 12 is typically a Cu wire having a thickness of about 3 μm. Vias 14, 14″ typically have a much smaller width than the metal wire inductors and they are typically comprised of W.
The dual-metal inductor shown in FIG. 1 is used in the industry to provide high performance in both series and parallel inductors for very high Q applications (peak Q of 28, 1 nH inductor, 3–4 GHz) and is driven by the sheet resistance of the metal wire inductors. Series inductance densities of 3–4× single devices are being achieved.
One major problem with the metal stacked inductor shown in FIG. 1 is that the inductor has a sheet resistance that is too high for use in many RF applications. The high sheet resistance of the prior art dual-metal stack inductor is caused by the presence of the W via that is used in interconnecting the top metal wire inductor to the bottom metal wire inductor. The resistance of the W via is much higher than that of metal wires.
Despite the above, there is a continued need for providing integrated metal stacked inductors that have a high quality factor Q (on the order of about 25 or above), yet have a substantially low sheet resistance (on the order of about 5 mOhms/square or less). Such integrated metal stacked inductors would be highly useful in RF applications, in particularly RF complementary metal oxide semiconductor (CMOS) and SiGe technologies.